The field of the invention relates to preparation of main memory read commands and more particularly to speculative read command preparation.
Low access latency is key to good microprocessor performance. The memory hierarchy of cache and dynamic random access memory (DRAM) is useful to help hide the relatively long latency of main memory. However, if the information sought by the microprocessor is not present in one of the caches, the microprocessor may stall while waiting for the request to return from the DRAM.
In a state of the art computer system, having both a first and second level cache as well as a main memory, an information request from the microprocessor is typically handled in the following manner. If a level one cache lookup fails, then a request is sent to a level two cache controller. A level two cache lookup is then performed. If the level two cache lookup fails then the request is finally sent to the main memory controller, which then forwards the request to main memory. Under this scenario, the potential for a main memory stall is great.
An alternate prior art approach has been to send a memory request to the main memory in parallel to the sending of a cache lookup request. The main memory is searched concurrently to the performance of the cache lookup. Although this approach can reduce latency, it has major drawbacks. Most significantly, it prevents other agents from accessing main memory and consumes bus bandwidth. In the event that the cache lookup is successful, then the energy and time spent to search main memory is wasted.
There is, therefore, a need for reducing main memory latency without generating many wasted memory transactions by preparing a speculative main memory read command.